The sequence of events that occur during interrupt processing is as follows.
1. An interrupt becomes active, either because
(a) the interrupt condition occurs (for example, a timer expires),
(b) a previously posted interrupt is enabled through an update of an interrupt mask register, or
(c) an interrupt is pending and GIE is set from ‘0’ to ‘1’ in the CPU Flag register.
2. The current executing instruction finishes.
2.當前執行的指令完成。
3. The internal interrupt routine executes, taking 13 cycles.
During this time, the following actions occur:
■ The PCH, PCL, and Flag register (CPU_F) are pushed onto the stack (in that order).
■ The CPU_F register is then cleared. Since this clears the GIE bit to 0, additional interrupts are temporarily disabled.
■ The PCH (PC[15:8]) is cleared to zero.
■ The interrupt vector is read from the interrupt controller and its value is placed into PCL (PC[7:0]). This sets the program counter to point to the appropriate address in the interrupt table (for example, 001Ch for
the GPIO interrupt).
4. Program execution vectors to the interrupt table. Typically, a LJMP instruction in the interrupt table sends execution to the user's interrupt service routine (ISR) for this interrupt. (See “Instruction Set Summary” on page 62.)
4。程序執行向量中斷表。通常情況下，在中斷表LJMP指令發送到用戶的中斷服務例程（ISR）的執行這個中斷。 （請參閱第62頁的“指令集匯總”）。
5. The ISR executes. Note that interrupts are disabled since GIE = 0. In the ISR, interrupts can be re-enabled if desired, by setting GIE = 1 (take care to avoid stack overflow in this case).
6. The ISR ends with a RETI instruction. This pops the Flag register, PCL, and PCH from the stack, restoring those registers. The restored Flag register re-enables interrupts, since GIE = 1 again.
7. Execution resumes at the next instruction, after the one that occurred before the interrupt. However, if there are more pending interrupts, the subsequent interrupts will be processed before the next normal program instruction.
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