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CYPRESS 中斷處理程序

The sequence of events that occur during interrupt processing is as follows.
1.   An interrupt becomes active, either because
(a) the interrupt condition occurs (for example, a timer expires),
(b) a previously posted interrupt is enabled through an update of an interrupt mask register, or
(c) an interrupt is pending and GIE is set from ‘0’ to ‘1’ in the CPU Flag register.

在中斷處理過程中所發生的事件的序列如下所示。
1。中斷變得活躍,要么是因為
(a)該中斷條件發生時(例如,一個定時器到期),
(b)在先前發布的中斷被允許時通過中斷屏蔽寄存器的更新,或
(c)在中斷掛起和GIE設置從'0'到'1'在CPU標誌寄存器。

2.   The current executing instruction finishes.
2.當前執行的指令完成。

3.  The internal interrupt routine executes, taking 13 cycles.
During this time, the following actions occur:
■    The PCH, PCL, and Flag register (CPU_F) are pushed onto the stack (in that order).
■    The CPU_F register is then cleared. Since this clears the GIE bit to 0, additional interrupts are temporarily disabled.
■    The PCH (PC[15:8]) is cleared to zero.
■    The interrupt vector is read from the interrupt controller and its value is placed into PCL (PC[7:0]). This sets the program counter to point to the appropriate address in the interrupt table (for example, 001Ch for
the GPIO interrupt).

3。內部執行中斷服務程序,13個週期。
在此期間,發生以下操作:
■PCH,PCL,和標誌寄存器(CPU_F)推入堆棧(按順序)。
■CPU_F寄存器然後清除。由於清除GIE位0,額外的中斷是暫時停用。
■PCH(PC[15:8])被清除為零。
■讀取中斷向量從中斷控制器,其值被放置到PCL(PC[7:0])。這設置程序計數器指向相應的地址在中斷表(例如,001CH
GPIO中斷)。

4.   Program execution vectors to the interrupt table. Typically, a LJMP instruction in the interrupt table sends execution to the user's interrupt service routine (ISR) for this interrupt. (See “Instruction Set Summary” on page 62.)
4。程序執行向量中斷表。通常情況下,在中斷表LJMP指令發送到用戶的中斷服務例程(ISR)的執行這個中斷。 (請參閱第62頁的“指令集匯總”)。


5.   The ISR executes. Note that interrupts are disabled since GIE = 0. In the ISR, interrupts can be re-enabled if desired, by setting GIE = 1 (take care to avoid stack overflow in this case).

5。 ISR執行。注意:因為GIE=0,中斷被禁止。在ISR,中斷可以重新啟用,如果需要的話,通過設置GIE=1(照顧,以避免在這種情況下,堆棧溢出)。

6.   The ISR ends with a RETI instruction. This pops the Flag register, PCL, and PCH from the stack, restoring those registers. The restored Flag register re-enables interrupts, since GIE = 1 again.

6。 ISR RETI指令結束。這從棧中彈出標誌寄存器,PCL和PCH,恢復這些寄存器。恢復標誌寄存器重新啟用中斷,因為GIE=1。

7.   Execution resumes at the next instruction, after the one that occurred before the interrupt. However, if there are more pending interrupts, the subsequent interrupts will be processed before the next normal program instruction.

7。恢復執行下一條指令後,之前發生中斷。但是,如果有更多的待處理中斷,隨後中斷將被處理之前,在下一個正常的程序指令。
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